1. Field of the Invention
The present invention relates to semiconductor devices.
2. Description of the Related Art
Semiconductor devices, more particularly, integrated circuits using metal oxide semiconductor (MOS) transistors are increasingly being highly integrated. In association with the increase in the degree of integration, miniaturization of the MOS transistors used in the integrated circuits has progressed to a region of nanometers. With the improved miniaturization of MOS transistors constituting inverter circuits as a basic circuitry for digital circuits, the following problems have arisen: difficulty in reducing leak currents; occurrence of reduction in reliability because of a hot carrier effect; and difficulty in reducing an area occupied by circuits due to a need to ensure a necessary amount of current. In order to solve such problems, surrounding gate transistors (SGTs) having a structure in which a source, a gate, and a drain are arranged in the vertical direction with respect to a substrate and in which the gate is formed around a silicon pillar have been proposed. Complementary MOS (CMOS) inverter circuits using a pMOS SGT and an nMOS SGT have been proposed (for example, “A Novel Circuit Technology with Surrounding Gate Transistors (SGT's) for Ultra High Density DRAM's”, S. Watanabe, K. Tsuchida, D. Takashima, Y. Oowaki, A. Nitayama, K. Hieda, H. Takato, K. Sunouchi, F. Horiguchi, K. Ohuchi, F. Masuoka, H. Hara, IEEE JSSC, Vol. 30, No. 9, 1995).
A static random access memory (SRAM) is constituted by two inverters and two selection transistors. When an SRAM is formed using a conventional SGT-based CMOS inverter circuits, the SRAM is constituted by two pMOS SGTs and four nMOS SGTs. In other words, the SRAM formed using the conventional SGT-based CMOS inverter circuits is constituted by a total of six pillars.